Hyper MISO Serial Peripheral Interface

Buffering high-resolution images with minimal latency is a cornerstone of real-time vision systems, facilitating efficient data transfer from buffers to processors in demanding applications such as autonomous vehicles, drones, robotics, Internet of Things (IoT), and industrial automation. Yet traditional protocols struggle to meet these demands. Inter-Integrated Circuit (I²C) lacks bandwidth; Controller Area Network (CAN) is robust but slow, and Serial Peripheral Interface (SPI), though faster, is constrained by its single-data-line architecture. High-speed protocols, such as Mobile Industry Processor Interface (MIPI) - Camera Serial Interface 2 (CSI-2), introduce significant complexity, cost, and power overhead, making them less suitable for lightweight embedded systems.

This paper introduces an alternative approach, leveraging a Hyper-Master in Slave Out (MISO) SPI architecture that enables parallel data reception across multiple lines, as shown in Fig. 1. This increases throughput without raising the SPI clock frequency, delivering a simple, scalable, and efficient solution for high-speed image and sensor data transmission in resource-constrained environments. Altair® DSim™ performed RTL simulation and verification, while Altair® Silicon Debug Tools™ supported schematic visualization and signal-level debugging.