Semiconductor companies face daunting challenges related to chip design and verification. These challenges include increased competition; larger, more complex designs; time-to-market pressures; and limited budgets for infrastructure and tools. Improvements in processor speed have slowed, causing organizations to look for new ways to improve efficiency. Physical design flows that push the power, performance, and area (PPA) envelope need to be fully repeatable and tuned for every aspect of the design block so an organization can retain the knowledge and recipe for future use. Altair® FlowTracer™ is a rare example of a flow manager that can have its flow redefined even as the flow is running.