3D IC and Thermal Aware Chiplet Floorplan

Iyad Rayane, Senior Technical Specialist Electronic System Design at Altair presents at the 2024 ATCx Electronics conference.

In this presentation, we explore the multifaceted challenges of 3D ICs, focusing on multiphysics issues arising from die stacking and floorplan-induced hotspots. We will show Altair SimLab advanced analysis and chiplets floorplan techniques to mitigate these challenges and enhance 3D IC reliability. We will examine the critical impact of these hotspots on package lamination, leading to warpage and thermal management complexities and how SimLab allows accurate analysis of the full ECAD models to prevent those risks.