< Back to Search Results

Increasing Electronic Design Automation (EDA) Performance and Throughput is Critical to Intel’s Silicon Design Engineers

Increasing Electronic Design Automation (EDA) Performance and Throughput is Critical to Intel’s Silicon Design Engineers

Silicon chip design engineers at Intel face ongoing challenges: integrating more features into ever-shrinking silicon chips, bringing products to market faster and keeping design engineering and manufacturing costs low. Design engineers run more than 273 million compute-intensive batch jobs every week. Each job takes from a few seconds to several days to complete.

As design complexity increases, so do the requirements for compute capacity, so refreshing servers and workstations with higher-performing systems is cost-effective and offers a competitive advantage by enabling faster chip design. Refreshing older servers also enables us to realize data center cost savings. By taking advantage of the performance and power-efficiency improvements in new server generations, we can increase computing capacity within the same data center footprint, helping to avoid expensive data center construction and reduce operational costs due to reduced power consumption.

To meet these engineers’ computing capacity requirements, Intel IT conducts ongoing throughput performance tests using real-world Intel silicon Design workloads. These tests measure EDA workload throughput and help us analyze the performance improvements—and in turn, business benefit offered by newer generations of Intel® processors.

For this discussion we will be sharing our latest test results and how increased EDA throughput performance improves the overall EDA design cycles and optimizes time to market of Intel® chips. Our test results suggest that other technical applications with large memory requirements—such as simulation and verification applications in the auto, aeronautical, oil and gas and life sciences industries—could see similar throughput improvements, depending on their workload characteristics.

Presented by Shesha Krishnapura, Intel Fellow, IT Chief Technology Officer| Intel, at the ATCx Electronics for Engineers in October 2023, 20.2 mins

Have a Question? If you need assistance beyond what is provided above, please contact us.